(1) Field of the Invention
The invention relates to integrated circuits. More specifically, the invention relates to a high-voltage tolerant high-voltage output buffer.
(2) Background
Technology advances in integrated circuit fabrication have led to more compact chip designs. Lower voltages processes come with the smaller size. CMOS devices are able to use low voltage power supplies to prevent damage to devices having small feature sizes, and to reduce the overall power consumption. For example, power supplies for CMOS devices are being reduced from 3.3 volts to 2.5 volts to 1.8 volts and lower. However, low voltage CMOS devices often interface with transistor-transistor logic (TTL) devices that operate at higher supply voltages, e.g., 5 volts. Unfortunately, given that the reduction in supply voltage is driven to large extent by the inability of smaller scaled devices to withstand higher voltages between the gate and source or drain, the design of input/output (I/O) buffers to interface to legacy (I/O) standards such as the Peripheral Component Interconnect (PCI) Specification, version 2.1, PCI Special Interest Group, 2575 NE Kathryn St. #17, Hillsboro, Oreg. 97124, December 1997 (PCI standard) is problematic. Frequently, additional transistors are added to the process which are essentially older-generation devices (with thicker gate oxides and longer channel lengths) specifically for the interface circuits. Such additional devices add process cost and complexity to the manufacturing process since additional processing steps are required to produce them. It is therefore desirable to produce a buffer capable of interfacing with higher legacy voltages without the need for extra process steps. Typically, such approaches have required the use of relatively complex circuit solutions involving stacked devices, where a stacked (cascode configuration) transistor protects a control transistor. Such stacks have limited drive due to high level shifting requirements and can be quite large, due to the additional device sizes (from the stacks) and additional circuit complexity.
The Peripheral Component Interconnect (PCI) bus standard, PCI Compliance Checklist, Revision 2.1, published Jan. 1, 1997, requires a minimum of 2.4 volts on the bus to identify a high transition. Typically, there are a large number of buffers and drivers tied to the bus, any of which can be a TTL device. Therefore, each device must be capable of driving at least 2.4 volts, and be able with withstand voltage levels as high as 6.5 volts for short durations, with S leads state levels of up to 5.5V.
Another issue with multiple supply voltages is that the different voltages have different characteristics. Some voltages may be stable before others. In a worst case scenario, the highest voltage, e.g., 5 volts, may stabilize first, and already be at its highest level while the other voltages, e.g., 3.3 volts and 1.8 volts, are still at ground or low level. Such an initial condition at power-up could expose low voltage CMOS devices to the full 5 volts. This can cause damage to the device or shorten its life. For example, this could damage the gate oxide in the transistors that are typically used in the devices. This situation can be exacerbated by the requirements of the PCI standard, which requires some of the PIN""s to power up at 5 volts.
In one embodiment, a series stack including a first and a second MOS vertical source drain (MVSD) transistor is coupled between a positive power supply and a pad is disclosed. The series stack has a central node. A p-driver including a first and a second p-type transistor is coupled in series with a source of the first p-type transistor coupled to a positive power supply. The drain of the second p-type transistor is coupled to the central node.